Structured arrays in data processing systems are generally tested using a scan path test methodology to provide a high level of controllability and observability during the testing operation. The scan path test methodology uses a serial shifting path to communicate test data between the array or logic circuit being tested and a test circuit.
In structured arrays, such as programmable logic arrays, random access memory, read only memory, and other array type structures, a sense amplifier is normally used to perform a bit line sensing function for each output of the array. In a data processing system which uses the scan path test methodology, each of the sense amplifiers provided for an array is followed by a master/slave test latch which is used to support scan path testing. Each of the master/slave test latches are coupled together to form a shift register structure which is used only during testing operations. The shift register structure is not used during normal operation of the data processing system.
The scan path testing methodology uses a following set of steps to verify the functionality of an associated array. In a first step, an input stimulus is provided to the array and the array is enabled. In a second step, each sense amplifier is enabled to sense the state of its corresponding output from the array. The state is subsequently stored in the associated master/slave test latch. In a third step, the master test latch shifts the output data into *the corresponding slave test latch. The slave test latch then shifts the output data into an adjacent master test latch in the same direction in a fourth step. The last slave test latch does not shift to a master test latch, but shifts the data onto a serial data path which leads to the test circuitry. The test circuitry may be located on or off of the integrated circuit. The third and fourth steps are repeated until all of the output data has been shifted to the test circuitry via the serial data path. The procedure is then repeated using a different input stimulus.
The example described above is one implementation of the scan path testing methodology. Other implementations do exist in which the function of the master test latch is performed by a sense amplifier such that circuitry required to test the integrated circuit is minimized. Such implementations of the scan path testing methodology are well known in the data processing art. Furthermore, in each implementation, test circuitry requires the use of slave test latches. Such slave test latches still require circuit area which is used only for testing purposes.
A dual scan path testing methodology has been developed which provides a more silicon efficient approach to the scan path testing methodology. In the dual scan path testing methodology, alternate latches are allowed to overwrite the data stored in the next adjacent latch. Thus, during a first scan test of the array outputs, the original data from the even latches is overwritten and the original data from the odd latches is scanned out via the serial data path. During a second scan test of the array outputs, the original data from the Odd latches is overwritten and the original data from the even latches is scanned out.
The dual scan path testing methodology described herein uses a sense amplifier to perform the single required latching function. The sense amplifier serves as a master or slave latch depending on which scan pass is performed. During the first pass, the odd outputs are scanned out with the corresponding odd sense amplifiers serving as the master portion of the shifter and the even sense amplifiers serving as the slave portion of the shifter. Conversely, during the second pass, the even outputs are scanned out with the corresponding even sense amplifiers serving as the master portion of the shifter and the odd sense amplifiers serving as the slave portion of the shifter. By using the sense amplifiers in addition to the dual scan path testing methodology, testing of an array in an integrated circuit may be performed using a minimal amount of both circuitry and power consumption.
The dual scan path testing methodology is typically implemented in an integrated circuit through a software program which is written and controlled externally. The software is repeated for each vector which is to be tested. While the dual scan path testing methodology reduces the amount of circuitry required to test an array in the integrated circuit, the software overhead required to implement the dual scan path testing methodology requires a significant number of clock cycles to process the appropriate software program.